1. Field of the Invention
The invention relates to a semiconductor device and fabrication thereof, and more particularly to a transistor of a semiconductor device and fabrication thereof.
2. Description of the Related Art
Integrated circuit technology continues to advance at a rapid pace, with many circuit technologies being implemented using semiconductor fabrication processes. Consideration is given to various aspects of the development of semiconductor fabrication processes, including, maximizing efficiency, lowering manufacturing cost, and increasing performance. With these goals in mind, reducing transistor size is a topic of continuing interest. Reduced transistor size enables reduced device size and facilitates improved device performance.
FIGS. 1A-1E show fabrications of a conventional transistor. First, referring to FIG. 1A, a gate dielectric layer 104, a gate electrode layer 106 and a hard mask layer 108 are sequentially formed on a silicon substrate 102. A photoresist layer (not shown) is formed on the hard mask layer 108 and then patterned by lithography to form a photoresist pattern 110. Referring to FIG. 1B, the hard mask layer 108 is patterned using the photoresist pattern 110 as a mask. The gate electrode layer 106 is then patterned using the patterned hard mask layer 108 as a mask. Referring to FIG. 1C, a first spacer 112 is formed on a sidewall of the gate electrode layer 106. Referring to FIG. 1D, the substrate 102 is implanted using the gate electrode layer 108 and the first spacer 112 as a mask to form a lightly doped region 114. Referring to FIG. 1E, a second spacer 118 is formed on a sidewall of the first spacer 112. Next, the substrate 102 is implanted to form a source/drain region 116 using gate electrode layer 108, the first spacer 112 and the second spacer 118 as a mask.
In the conventional technology, the short channel effect (SCE) is among the most challenging design obstacles to be overcome in scaling down critical dimensions of devices. Various forms of SCE include, threshold Voltage (VT) rolloff, drain induced barrier lowering (DIBL), and subthreshold swing variation. Another problem related to SCE is an increase of gate-to-drain overlap capacitance, resulting in slower circuits.
A few of the parameters that can be optimized for reducing SCE are source and drain (S/D) 116 extension junction depth and channel doping. Because the LDD implant region 114, also referred to as the source and drain extension (SDE) implant region, is self-aligned to the edge of gate 106, inserting a first spacer 112 adjacent the gate 106 edge prior to performing an LDD implant can compensate the spacing due to lateral diffusion of dopants and reduce the gate-to-drain overlap capacitance.
As gate lengths become shorter, for example less than about 0.1 microns including less than about 65 nm, the conventional processes with one spacer formation for forming the LDD and S/D doped regions are no longer adequate to precisely position the LDD implant regions 114, thereby leading to increased SCE.